Welcome to the FPGA design flow and example design. In the first module, we introduced programmable logic devices and the FPGA. In Module 2, we used Quartus Prime to work through a sample FPGA design, using the design flow shown here. You will be learning by doing. The design begins with the design entry, continues with simulation to verify the logic is implemented as expected, and then the tool will perform synthesis, also called mapping, to map the logic to the device architecture. Next, the tool would create the Internet connection between cells by placing a routing or fitting of the design. Timing analysis using static timing tools is then required to assure there are no setup or hole violations in the design. Running another simulation after fitting is done is a good practice and can uncover timing issues. If analysis confirms proper operation of the circuit, the next step is to use the tool to create a programming file, which is then downloaded into the FPGA device for testing. There are lots of ways to create an FPGA design to describe the logic that it implements. Quartus Prime provides a number of methods for schematic entry, including schematic capture, import of IP blocks, HDL text entr,y including VHDL, Verilog, and System-Verilog, state machine entry, and import of EDIF files. We will show you that you can use multiple methods of defining the design in the same project, that these methods can be mixed and matched. Quartus Prime's analysis and synthesis module checks the design source files for errors, builds a database that puts all the design files in a hierarchy, synthesizes and optimizes the logic design, and maps the design logic to device resources. Fitting the design into the smallest possible part is a principal design challenge in FPGA design. Quartus Prime allows control of the fitting process by choice of fitting approaches, including balanced, high performance for speed, low power, and small area. Quartus Prime can provide several views of the designing pictures, representing different aspects of the design. Picture representations of the design from RTL Viewer or the Technology Map Viewer can give you confidence in your design implementation and design techniques, and help you develop an intuitive sense of the design, particularly if you are an experienced hardware designer. The Chip Planner provides a picture of the chip, showing the use of the design resources. This view can be very helpful in locating problem areas during debugging. Synchronization is fundamental to reliable FPGA designs. The synchronizing signal is the clock. Static timing analysis can determine if there are violations of timing requirements relative to the clock. It is the primary tool for achieving timing closure, a necessity for any and all FPGA designs. The TimeQuest timing analyzer uses a set of equations to calculate slack, and also to determine Fmax, an important metric in FPGA performance. It can be guided by a set of rules known as constraints, which also help the fitter to optimize the timing driven design. We will learn how to write effective constraints to improve the Fmax. ModelSim is a powerful simulation tool integrated with Quartus Prime. It can create accurate timing diagrams of all the signals in a design, as well as stimulus signals for testing. We will use this tool to test and better understand the operation of our example design. Results will be displayed as a timing diagram, like the one shown. In summary, we will learn about the FPGA design flow by doing a example design in detail using Quartus Prime. Videos in this module will cover the FPGA design flow, downloading Quartus Prime, installing Quartus Prime, introducing Quartus Prime, create a design project in Quartus Prime, create a top-level design in Quartus Prime. Compile a design, view the RTL, Timing Analysis with TimeQuest Part I, Timing Analysis with TimeQuest Part II, and simulate an FPGA design with ModelSim.